Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 69, Issue 1, Pages 120-126Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3130011
Keywords
Thin film transistors; Logic gates; Insulators; Nonvolatile memory; Transistors; Programming; Electrodes; InGaZnO; InZnSnO; nonvolatile memory (NVM); thin-film transistor (TFT)
Funding
- National Research Foundation of Korea (NRF) - Korea Government (MSIT) [NRF-2020M3H4A3081897]
- National Research Foundation of Korea [2020M3H4A3081897] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
Ask authors/readers for more resources
This study improved memory erase speed in amorphous oxide semiconductor memory thin-film transistor (TFT) by introducing new double-gate and body-contacted memory structures.
In this study, we present programming speed enhancement in amorphous oxide semiconductor memory thin-film transistor (TFT). We developed a nonvolatile memory transistor based on InZnSnO back-channel-etch TFT with InGaZnO charge storage layer inserted between gate insulators. We proposed double-gate (DG) and body-contacted (BC) memory structure to improve memory erase speed, which is the most important issue in oxide memory TFTs. DG memory did not show sufficient improvement due to large voltage drop in second gate insulator. BC memory, which can control back-channel potential directly, showed significant improvement on memory program/erase speed.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available
Share Paper
