Efficient Modeling of Charge Trapping a Cryogenic Temperatures-Part II: Experimental

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high-k CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO2 and HfO2 layer. We show that NBTI is dominated by defects in the SiO2 layer, whereas PBTI arises mainly from defects in the HfO2 layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site.

Automated summary

Through experimental results and a quantum mechanical model, we found that at low temperatures, the BTI of pMOSFETs is mainly affected by the SiO2 layer, while the BTI of nMOSFETs is mainly affected by the HfO2 layer, and defects in the HfO2 layer do not freeze out at low temperatures.