Journal
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume 21, Issue 4, Pages 603-607Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TDMR.2021.3121063
Keywords
Degradation; Voltage measurement; Stress; Switches; Analytical models; Time measurement; Reactive power; RRAM; analytical read-disturb model; cycling effect
Funding
- Ministry of Science and Technology (MOST), Taiwan [MOST-108-2221-E-009-009-MY2]
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The study reveals that read-disturb failure time in the low resistance state of a hafnium-oxide resistive memory cell degrades significantly after SET/RESET cycling. An analytical model is developed to describe this degradation, and it shows good agreement with measured results. Different read failure criteria also have an impact on read-disturb failure time in post-cycling cells.
We characterize SET/RESET cycling effects on read-disturb failure time in the low resistance state (LRS) of a hafnium-oxide resistive memory cell. We find that the read-disturb failure time degrades by orders of magnitude after SET/RESET cycling. An analytical LRS read-disturb failure time model including cycling induced trap generation rate and its influence on read-disturb characteristics is developed. We compare our read-disturb model with measured results in a wide range of read voltage and SET/RESET cycle number. Good agreement between modeled and measurement results is obtained. We evaluate read-disturb failure time in post-cycling cells for different read failure criteria.
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