4.7 Article

Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding

Journal

IEEE TRANSACTIONS ON COMMUNICATIONS
Volume 70, Issue 4, Pages 2213-2226

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCOMM.2022.3149913

Keywords

Decoding; Table lookup; Iterative decoding; Quantization (signal); Field programmable gate arrays; Hardware; Floods; LDPC decoder; low bit width decoding; hardware efficiency; layered decoding; FPGA

Funding

  1. National Science Foundation (NSF) [CCF-1911166]
  2. SA Photonics [DOI: 10.1109/GLOBECOM42002.2020.9348139, GLOBECOM46510.2021.9685732]

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This paper uses the RCQ paradigm to decode LDPC codes and introduces new methods such as layer-specific RCQ and layered discrete density evolution. Simulation results show that these methods can improve decoding performance while reducing storage and resource consumption.
This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.

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