Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 69, Issue 2, Pages 269-273Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2021.3105552
Keywords
Voltage-controlled oscillator; phase-locked loop; sub-sampling; delay-locked loop; jitter; phase noise
Categories
Funding
- Intelligent & Sustainable Medical Electronics Research Fund in National Taiwan University
- Ministry of Science and Technology, Taipei, Taiwan
Ask authors/readers for more resources
A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is proposed to extend the loop bandwidth and achieve low jitter.
A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a 0.18 mu m CMOS process and its active area is 0.185mm(2). At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of -111.83dBc/Hz and -116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is -50.3dBc.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available