A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes

This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses V $_{{CM}}$ -based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm(2). At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are -0.65/+0.45 and -2.2/+2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.

Automated summary

This paper presents a 16-bit ADC with excellent SFDR, utilizing special DAC switching schemes and capacitor swapping scheme to enhance performance. The measured results demonstrate that the ADC performs well in various metrics, with small size and low power consumption.