Related references
Note: Only part of the references are listed.A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration
Dong-Jin Chang et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2021)
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
Meng Ni et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2021)
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration
Mingqiang Guo et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2020)
A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier
Shubin Liu et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2020)
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
Ahmed M. A. Ali et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2020)
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS
Athanasios T. Ramkaj et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2020)
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration
Dengquan Li et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2019)
A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration
Xiao Wang et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2019)
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC
Yuan Zhou et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2019)
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration
Jeonggoo Song et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2019)
A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs
Armia Salib et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2019)
A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique
Chin-Yu Lin et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2018)
A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme
Hyun-Wook Kang et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2018)
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation
Jae-Won Nam et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2018)
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS
Benwei Xu et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2017)
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
Siddharth Devarajan et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2017)
Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition
Han Le Duc et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2017)
Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs
Hamidreza Mafi et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2017)
A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs
Yunsoo Park et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2016)
A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS
Dusan Stepanovic et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2013)
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications
Aida Varzaghani et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2013)
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration
Manar El-Chammas et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2011)
Share Paper
