An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of half-bridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 mu m technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of 70 mu m x 180 mu m. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

Automated summary

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of half-bridge converter switches, reducing losses and mitigating shoot-through current. Implemented in AMS 0.35 μm technology, the proposed circuit greatly decreases power losses in the half-bridge circuit.