Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 69, Issue 9, Pages 3501-3511Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2022.3141087
Keywords
Logic gates; Decoding; Memristors; Switches; Multivalued logic; Field programmable gate arrays; Microdisplays; FPGA; logic; memristor; multilevel; RRAM; synthesis; ternary
Categories
Funding
- National Natural Science Foundation of China [61871429]
- Natural Science Foundation of Zhejiang Province [LY18F010012]
- Fundamental Research Funds for the Provincial Universities of Zhejiang [GK219909299001-413]
- UC Santa Cruz Faculty Research Award
- Forrest Research Foundation
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The search for a compatible application of memristor-CMOS logic gates has been difficult due to slow switching speeds and resistive dissipation. However, in the context of active matrix displays with comparatively slower refresh rates, memristor-CMOS logic shows potential for peripheral I/O logic. In this study, ternary decoders were designed and implemented for a seven segment LED display, demonstrating improved data density.
The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25-240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1-3 line decoder and a ternary 2-9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.
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