4.7 Article

Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics

Journal

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2021.3100138

Keywords

Thin film transistors; Transistors; Zinc oxide; II-VI semiconductor materials; Inverters; Logic gates; Logic circuits; Custom logic; flexible circuits; ratioed logic; pass transistor logic; ITO-Stabilized ZnO TFT

Funding

  1. National Natural Science Foundation of China [61974095]
  2. Natural Science Foundation of Guangdong Province, China [2021A1515011162, 2019A1515012127]
  3. Research and Development Project of Key Areas of Guangdong Province, China [2053812200006]

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This paper presents general logic cell and module designs in basic digital signal processing for transparent, flexible chips and wearable electronics. Modified circuits based on n-type-only indium tin oxide stabilized ZnO thin-film transistors process are proposed to improve circuit performance. The circuits demonstrate smaller area with relatively moderate-high performance, promising building blocks for transparent flexible DSP electronics with low-speed requirements.
In this paper, general logic cell and module designs in basic digital signal processing (DSP), for transparent, flexible chips and wearable electronics are presented. Modified Circuits from ratioed logic and pass transistor logic styles are modified and proposed, based on n-type-only indium tin oxide (ITO) stabilized ZnO thin-film transistors (TFTs) process. Elaborations on logic circuits with purely n-type TFT transistors were carried out to extend the logic swing of circuit outputs and accelerate the signal propagation in complex logic functions with simplified pull-up/pull-down or passive networks. To implement logic complexes on multiple OR-of-ANDs functions with better performance, tailored active controlled ratioed logic style is adopted with faster speed and smaller area by simplifying the transistor networks properly. All the circuits were fabricated on transparent glass plate. The featured 2-input/3-input XOR gate, 4-1 MUX and D flip flop (DFF) can operate with maximum featured delays of 2-6 mu s at 5 V power supply, with comparatively over 50% less delays and areas than other state-of-art works. The featured 4-bit adder performs maximum 16.41 mu s delay at 5 V in measurement. A 4-bit multiplier is also presented based on the adder and DFF. These proposed TFT circuits exhibited smaller area with relatively moderate-high performance in comparison, which were promising building blocks for transparent flexible DSP electronics with low-speed requirements.

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