Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 56, Issue 11, Pages 3424-3433Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2021.3086853
Keywords
Delta Sigma analog-to-digital converter (ADC); data converter; multistage noise-shaping (MASH); noise-shaping successive approximation register (NS-SAR) ADC; pipelined SAR ADC
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Funding
- Samsung Science & Technology Foundation [SRFC-IT1092-C4]
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The pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure achieves high resolution and wide bandwidth while greatly relaxing the design requirements of each SAR quantizer, resulting in good power efficiency.
A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoM(S,DR)) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.
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