Journal
IEEE ELECTRON DEVICE LETTERS
Volume 43, Issue 4, Pages 549-552Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2022.3149029
Keywords
Capacitor-based synaptic device; capacitive neural network; MOS capacitor; NAND flash memory; neuromorphic system; spiking neural network (SNN)
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Funding
- NRF through the Korean Government [2020M3F3A2A01081656]
- Brain Korea 21 Four Project
- National Research Foundation of Korea [2020M3F3A2A01081656] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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This work presents a hardware neural network using capacitor-based synaptic devices. A MOS capacitor structure with a charge trapping layer was developed for the capacitor-based synaptic device. By using the charge occurring during the capacitor's charging and discharging process, multilevel weight values can be implemented. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.
In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear C- V characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.
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