Interface Engineering for 3-Bit per Cell Multilevel Resistive Switching in AlN Based Memristor

Gradual conduction tuning with a large memory window is essential for realizing multilevel switching memristive devices. In this work, we demonstrated 3-bit per cell storage capability with excellent endurance and retention behavior of AlN/AlO memristor via interface engineering. By incorporating an ultra-thin 2 nmAl(2)O(3) interface layer, seven distinct high resistance states with same low resistance state were achieved by controlling reset-stop voltage. In addition, by varying set compliance current, six resistance states with reliability and reproducibility were illustrated. The maximum cycle-to-cycle variability sigma/mu (standard deviation/mean) of any resistance statewas 28.7% in reset-stop voltage control methods. The multilevelswitching characteristics could be attributed to (a) enhancement of on-off ratio resulted due to insertion of Al2O3 barrier layer acts as series resistance (b) the gradual electron detrapping from occupied trap sites resulting in multiple intermediate resistance states during reset.

Automated summary

This work demonstrates the achievement of 3-bit per cell storage capability in AlN/AlO memristors through interface engineering, showcasing seven distinct high resistance states and one low resistance state by controlling reset-stop voltage, as well as six resistance states with reliability and reproducibility by varying set compliance current.