4.6 Article

Variation-Tolerant Capacitive Array for Binarized Neural Network

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 43, Issue 3, Pages 478-481

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2022.3143140

Keywords

Capacitance; Capacitance-voltage characteristics; Synapses; Neural networks; Convolutional neural networks; Memory management; Training; Capacitive neural network; neural network hardware; synaptic device; variation tolerance

Funding

  1. Technology Innovation Program - Ministry of Trade, Industry & Energy (MOTIE, South Korea) [20009972]
  2. National Research Foundation of Korea (NRF) - Korean Government
  3. Korea Evaluation Institute of Industrial Technology (KEIT) [20009972] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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This letter proposes a variation-tolerant capacitive binarized neural network using 2-terminal MANOS memory devices. The capacitance-voltage characteristic of the synaptic device is used to represent the weight of the binarized neural network. The proposed synaptic device shows less capacitance variation compared to conventional synaptic devices, resulting in a more robust network.
In this letter, we propose the variation-tolerant capacitive binarized neural network using the capacitance of 2-terminal MANOS memory devices. The capacitance-voltage characteristic of the synaptic device is shifted by program or erase operation. Two saturated regions of the C-V curve are used for representing the weight of the binarized neural network (BNN), 1 and -1. Thus, the capacitance variation of the proposed synaptic device is much less than the conductance variation of the conventional synaptic devices. The effects of V-th variation and memory window on accuracy are analyzed with CIFAR10 datasets. Our simulation result shows that the proposed capacitance-based BNN is much more robust to V-th variation compared to the conductance-based BNN.

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