High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor With Top Gate to Drain Offset

We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top- gate (TG) drain offset (L-TG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of similar to 10(7), subthreshold swing of 0.23 V/dec, and field-effect mobility (mu(FE)) of 14.6 cm(2)/Vs when L-TG(Off) is 5 mu m, which is 30% reduction compared to the conventional DG TFT with no drain offset (mu(FE) = 20.9 cm(2)/Vs). The Technologycomputer-aided design simulation indicates the electron concentration of similar to 10(16)/cm(3) at the offset region near top gate insulator/a-IGZO interface when L-TG(Off) is 5 mu m. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.

Automated summary

This study reports a dual-gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset structure. The TFT demonstrates a high on/off current ratio, subthreshold swing, and field-effect mobility, and exhibits stable performance.