Journal
IEEE ELECTRON DEVICE LETTERS
Volume 43, Issue 2, Pages 304-307Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2021.3139574
Keywords
Three-dimensional displays; FeFETs; Iron; Transistors; Threshold voltage; Solid modeling; Computer architecture; Ferroelectric transistor; 3D AND-type; compute-in-memory; vector-matrix multiplication (VMM); phase variation; deep neural network
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Funding
- Applications and Systems-Driven Center for Energy-Efficient Integrated NanoTechnologies (ASCENT), one of the semiconductor research corporation (SRC)/Defense Advanced Research Projects Agency (DARPA) Joint University Microelectronics Program (JUMP) Centers
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This paper proposes a 3D AND architecture based on FeFETs for the VMM of compute-in-memory paradigm. The architecture allows multibit weight with controllable linearity and multibit input through parallel connection of cells. Furthermore, the impact of phase variation of the ferroelectric layer on inference accuracy is examined.
Three-dimensional AND-type architecture (3D AND) based on ferroelectric field-effect transistors (FeFETs) is proposed for the vector-matrix multiplication (VMM) of compute-in-memory paradigm. By leveraging a vertical string as one synaptic element, multibit weight with controllable linearity is realized due to parallel connection of cells in a string. Multibit input is also feasible with appropriate word line (WL) biasing. To guarantee the deep neural network performance, the device-level conductance distribution should be tightened. The phase variation of ferroelectric layer is regarded as a primary variation source, and its impact on the inference accuracy is examined.
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