Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 63, Issue 7, Pages 638-642Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2016.2530148
Keywords
Delta-sampling; low power; successive approximation register analog-to-digital converter (SAR ADC)
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Funding
- A*STAR (Agency for Science, Technology and Research) SERC (Science and Engineering Research Council), Singapore [102 171 0163]
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This brief presents a novel analog-to-digital converter (ADC) with adaptive delta-sampling for ultra-low power sensing applications. By sampling only the incremental value of the input signal and adaptively adjusting the sampling frequency, the proposed ADC can achieve the same resolution and conversion range with less number of bits than the conventional ADC. Meanwhile, the power consumption is also very much reduced. The proposed 8-bit ADC is fabricated in a 0.18-mu m CMOS technology. It achieves 7.3 effective number of bits at an adaptive sampling frequency of 20 kHz/2 kHz, consuming only 151 nW for a neural signal acquisition application.
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