Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 63, Issue 12, Pages 2357-2367Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2016.2611645
Keywords
Coordinate descent; equalization; FPGA design; massive multi-user (MU) MIMO; orthogonal frequency-division multiplexing (OFDM); soft-output data detection
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Funding
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [1535897] Funding Source: National Science Foundation
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1232274] Funding Source: National Science Foundation
- Div Of Electrical, Commun & Cyber Sys
- Directorate For Engineering [1408006] Funding Source: National Science Foundation
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Data detection in massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems is among the most critical tasks due to the excessively high implementation complexity. In this paper, we propose a novel, equalization-based soft-output data-detection algorithm and corresponding reference FPGA designs for wideband massive MU-MIMO systems that use orthogonal frequency-division multiplexing (OFDM). Our data-detection algorithm performs approximate minimum mean-square error (MMSE) or box-constrained equalization using coordinate descent. We deploy a variety of algorithm-level optimizations that enable near-optimal error-rate performance at low implementation complexity, even for systems with hundreds of base-station (BS) antennas and thousands of subcarriers. We design a parallel VLSI architecture that uses pipeline inter-leaving and can be parametrized at design time to support various antenna configurations. We develop reference FPGA designs for massive MU-MIMO-OFDM systems and provide an extensive comparison to existing designs in terms of implementation complexity, throughput, and error-rate performance. For a 128 BS antenna, 8-user massive MU-MIMO-OFDM system, our FPGA design outperforms the next-best implementation by more than 2.6x in terms of throughput per FPGA look-up tables.
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