4.4 Article

An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant-Based Search Algorithm in HEVC

Journal

CIRCUITS SYSTEMS AND SIGNAL PROCESSING
Volume 41, Issue 3, Pages 1751-1774

Publisher

SPRINGER BIRKHAUSER
DOI: 10.1007/s00034-021-01850-2

Keywords

Quadrant-based search algorithm; Zero motion prejudgment; High efficiency video coding (HEVC); FPGA; Verilog HDL; PSNR; Motion estimation value; Sum of absolute difference (SAD) value; Power consumption; Operating frequency

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In this paper, a new quadrant-based search algorithm for motion estimation in HEVC standard is proposed, utilizing zero motion prejudgment and implemented on FPGA hardware platform. By reducing computational complexity and power consumption, the proposed model shows superior efficiency compared to existing algorithms. The experimental outcomes highlight the effectiveness of the proposed motion evaluation approach in HEVC.
In this manuscript, new quadrant-based search algorithm with zero motion prejudgment is proposed for motion estimation (ME) in HEVC (High Efficiency Video Coding) standard. The HEVC standard is used to obtain efficient output with low motion estimation time. The proposed quadrant-based search algorithm is a fast block matching algorithm that obtain better block matching amid the current block and reference block. The zero motion prejudgment (ZMP) method is used to find the block, whether it is motion or static and it is used for decreasing the computational complexity (CC) in the proposed quadrant-based search algorithm. The proposed quadrant-based search algorithm with ZMP technique for motion estimation in HEVC is implemented on the FPGA hardware platform. The entire architecture is executed in Verilog HDL with Virtex-5 technology and integrated with Xilinx ISE Design Suite 14.5. The results are integrated into the CIF (352 x 288 pixels) and HD (1280 x 720 pixels) video input sequence. The evaluation metrics like PSNR, Motion estimation time, sum of absolute difference (SAD) value are analyzed with existing method like hexagon, adaptive root pattern algorithm, and diamond search algorithm. Then the hardware parameters like power consumption and maximum operating frequency are measured. The hardware utilization is reduced and the power consumption of the proposed model is diminished to 0.143 W. The maximal operating frequency of the proposed model is 440.470 MHz. The experimental outcomes demonstrate that the proposed motion evaluation approach in HEVC is more effective than existing algorithms.

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