Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 51, Issue 12, Pages 2951-2962Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2016.2591553
Keywords
Analog-to-digital converter (ADC); Delta sigma converter; SAR; successive approximation
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A 0.076 mm(2) 12b 28 nm 600 MS/s 4-way time interleaved ADC with on chip buffer is presented. The usage of a subranging scheme consisting of a coarse SAR ADC followed by an incremental Delta Sigma fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The ADC area has been optimized by using a segmented charge-sharing charge-redistribution DAC. The prototype achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming 26 mW.
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