4.6 Article

A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture

Journal

IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 51, Issue 9, Pages 2091-2105

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2016.2582509

Keywords

Wireless sensor networks; radio frequency integrated circuits; wake-up receiver; ultra-low power; N-path filters; interferer resilient

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A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dual-conversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of -97 dBm and a carrier-to-interferer ratio better than -27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10(-3) bit error rate, while consuming 99 mu W from a 0.5 V voltage supply under continuous operation.

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