Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 51, Issue 10, Pages 2345-2356Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2016.2582854
Keywords
digital phase-locked-loop (PLL); frequency synthesizer; time-to-digital converter (TDC); successive-approximation-register analog-to-digital converter (SAR-ADC); sub-picosecond resolution; digitally controlled oscillator (DCO),least-mean-square (LMS); CMOS
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This paper presents a fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A Delta Sigma-less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm(2) and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.
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