Journal
IEEE ELECTRON DEVICE LETTERS
Volume 37, Issue 4, Pages 396-399Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2016.2527689
Keywords
Aluminum oxide phosphate (ALPO); cadmium telluride nanoparticle (CdTe-NP); floating gate memory; metal oxide nanoparticle oxide semiconductor devices (m-MONOS); high speed capacitance-voltage (HSCV)
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Funding
- Center for Nano Science and Engineering, Indian Institute of Science, Bengaluru, India
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We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.
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