Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia-essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

Automated summary

There is uncertainty about the future scalability of DRAM and its ability to meet the needs of next-generation systems. Therefore, researchers have been investing significant effort into the development of novel memory technologies. Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the potential candidates for next-generation memory, offering comparable capacity, frequency, and device size to DRAM. However, the academic research on STT-MRAM main memory remains limited, mainly due to the lack of publicly available detailed timing and current parameters. This study presents a method for cycle accurate simulation of STT-MRAM main memory and releases detailed timing and current parameters, enabling researchers to conduct reliable system-level simulation of STT-MRAM.