Journal
ELECTRONICS
Volume 10, Issue 15, Pages -Publisher
MDPI
DOI: 10.3390/electronics10151816
Keywords
TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronics
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Funding
- Spanish Ministerio de Economia y Competitividad (MINECO) [TEC2015-66002-R]
- State Agency for Research of the Spanish Ministry of Science and Innovation through the Unit of Excellence Maria de Maeztu 2020-2023 [CEX2019-000918-M]
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This paper presents a highly configurable 16-channel TDC ASIC with features such as time-of-flight and time-over-threshold measurements. The novel design of clock interpolation circuitry and the capability to operate at different supply voltages and frequencies offer a compromise between resolution and power consumption.
This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm(2). The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption.
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