Journal
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY
Volume 10, Issue 6, Pages -Publisher
ELECTROCHEMICAL SOC INC
DOI: 10.1149/2162-8777/ac08dd
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Funding
- Academy of Integrated Circuit Innovation [Y7YC01X001]
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In this study, FeFETs with replacement metal gate process were fabricated and the influence of gate length, gate width, and annealing temperature on memory window was investigated. The results showed the significant impact of fringe effect and interface trap density on FeFET performance.
In this study, the ferroelectric field-effect-transistor (FeFET) with replacement metal gate process was fabricated. The FeFETs with various gate lengths (L-G) and gate widths (W-G) were investigated, and large average memory window (MW), up to 2.4 V for various L-G and W-G, was achieved. The influence of L-G on MW was investigated. The experimental results show the MW of FeFET increases with decreasing of L-G due to fringe effect. Thus, in the design of FeFET, fringe effect must be considered carefully. The influence of annealing temperature on MW of FeFETs was also investigated. The experimental results show that there are similar MW values for various annealing temperatures due to low density of the interface trap. Furthermore, an artificial electronic synapse based on our FeFETs is demonstrated to mimic synaptic response by applying voltage pulses to their gates. FeFET synapse achieves weight update with small nonlinearity (alpha (p) = -0.071, alpha (d) = -0.095) and asymmetry ( divide alpha (p) -alpha (d) divide = 0.166). The influence of L-G on synaptic properties was also investigated. Artificial neural network (ANN) simulation based on the electronic synaptic arrays using the hand written digits data sets demonstrates a high recognition accuracy of 95.2%, and the influence of L-G on recognition accury of ANN was discussed finally.
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