A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

This work presents a low-power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon-based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and-Hold Amplifier (SHA) to reduce the power consumption. The memory effect in the proposed ADC is eliminated by a low input capacitance variable g(m) op-amp. The differential and integral nonlinearity of the converter is within LSB. Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2 MHz, 1-V-p-p,V- diff input signal while consuming only 7.3mW power from 1.8V supply.

Automated summary

This work presents a low-power 10-bit 40 MSPS Pipelined ADC with high SFDR and SNDR achieved while consuming only 7.3mW power.