4.4 Article

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

Journal

MEASUREMENT & CONTROL
Volume 55, Issue 1-2, Pages 3-12

Publisher

SAGE PUBLICATIONS LTD
DOI: 10.1177/00202940211029335

Keywords

Phase-locked loop; automatic parasitic capacitance cancellation; automatic gain control; Butterworth-Van Dyke equivalent circuit model; motional series resonant frequency

Funding

  1. Electronics and Telecommunications Research Institute (ETRI) - Korean government [20ZB1155]
  2. Defense Acquisition Program Administration
  3. Agency for Defense Development [UD190018ID]

Ask authors/readers for more resources

This paper presents a new type of PLL-based resonator driving IC with automatic parasitic capacitance cancellation and automatic gain control functions. The study has employed various techniques to compensate and cancel the distortion in the frequency response of the resonator.
This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth-Van Dyke equivalent circuit model with motional resistance of 72.8 k omega, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-mu m bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm(2). The simulated phase noise is -61.1 dBc/Hz at 1 kHz and the quality factor (Q-factor) is 59,590.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.4
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available