4.8 Article

Full Custom Design of an Arbitrary Waveform Gate Driver With 10-GHz Waypoint Rates for GaN FETs

Journal

IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 36, Issue 7, Pages 8267-8279

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2020.3044874

Keywords

Clocks; Logic gates; Gate drivers; Transient analysis; Gallium nitride; Integrated circuits; Switches; Active gate driving; CMOS integrated circuits; driver circuits; EMI reduction; gallium nitride (GaN); GHz arbitrary waveform generator

Funding

  1. UK Engineering and Physical Sciences Research Council (EPSRC) [EP/K021273/1, EP/R029504/1]
  2. EPSRC [EP/R029504/1, EP/K021273/1] Funding Source: UKRI

Ask authors/readers for more resources

This article describes the implementation details of a digitally programmable arbitrary waveform gate driver capable of high timing resolution, operating reliably under 400V gallium nitride (GaN) bridge leg.
Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. This article describes, for the first time, the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10-GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the tradeoff in flexibility, speed, and area. The design, which is taped out in a 180-nm high-voltage CMOS process, utilizes buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock speed of high-voltage silicon integrated circuits and a fully digital architecture to provide robustness under high slew rates of the ground rail. The driver IC has networks of 100-ps delay elements that are configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering, and pulse generation. The driver IC is experimentally evaluated to have a 100-ps resolution and to operate reliably in a 400-V gallium nitride (GaN) bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.

Authors

I am an author on this paper
Click your name to claim this paper and add it to your profile.

Reviews

Primary Rating

4.8
Not enough ratings

Secondary Ratings

Novelty
-
Significance
-
Scientific rigor
-
Rate this paper

Recommended

No Data Available
No Data Available