4.8 Article

Switched-Capacitor-Based Modular T-Type Inverter

Journal

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 68, Issue 7, Pages 5725-5732

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2020.2992963

Keywords

Inverters; Switches; Topology; Capacitors; MOSFET; Boosting; Switching circuits; Multilevel inverter; switched capacitor; T-type inverter; voltage boosting

Funding

  1. Korea Institute of Energy Technology Evaluation and Planning (KETEP)
  2. Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea [20194030202370, 20182410105160]
  3. Korea Evaluation Institute of Industrial Technology (KEIT) [20182410105160] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

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A novel topology of multilevel inverters is proposed in this study, which successfully reduces common-mode voltage by connecting the neutral of the ac output to the midpoint of the dc link. All switched-capacitors are ensured to be charged for at least half of the fundamental period, alleviating capacitor voltage ripples and current spikes.
Switched-capacitor-based multilevel inverters have been gaining increasing attention in recent years in view of their voltage-boosting capability and capacitor self-balancing properties. However, the existing topologies, which comprise frontend switched-capacitor cells and a backend H-bridge, result in longer discharging duration in some of their switched-capacitors. In addition, the adoption of backend H-bridge introduces common-mode voltage and necessitates multiple dc sources for voltage level extension. To resolve these problems, this article proposes a novel topology comprises a T-type inverter and n cascaded switched-capacitor cells. It requires only a single dc source and it manages to mitigate the common-mode voltage by connecting the neutral of ac output to the mid-point of dc link. All switched-capacitors in the proposed topology are ensured to be charged for at least half of the fundamental period to alleviate the capacitor voltage ripples and current spikes. The operation of the proposed topology is analyzed and experimental results are presented for validation.

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