A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

In this article a review of low temperature (LT) (<= 500 degrees C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 degrees C during a couple of hours. Then, the full LT process flow with process modules developed at 500 degrees C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low-k (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 degrees C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 degrees C thermal budget (TB) is highlighted.

Automated summary

This article reviews the application and progress of low temperature process modules in 3-D sequential integration, showcasing breakthroughs in high performance digital stacked FETs. By overcoming previous potential barriers, a comprehensive low temperature process has been achieved.