Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 68, Issue 8, Pages 3930-3935Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3084578
Keywords
di/dt; gate voltage overshoot; lateral insulated gate bipolar transistor (LIGBT); ON-state voltage; silicon-on-insulator (SOI); SOI-LIGBT; turn-on loss; U-shaped channel
Funding
- National Natural Science Foundation of China [61804026, 61874026]
- Natural Science Foundation of Jiangsu Province [BK20191262]
- National Key Research and Development Plan [2017YFB0402904]
- Key Research and Development Plan of Jiangsu [BE2018003-3]
- Fundamental Research Funds for the Central Universities
- Joint Fund for the Pre-Research of Equipment [6141A02022427]
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This article investigates the gate voltage overshoot during the turn-on transient in the trench gate U-shaped (TGU) channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) and proposes novel structures for the first time with numerical simulation. The novel structures can suppress hole accumulation, slow down the rise of electric potential near G(2), lower di/dt, and shield the displacement current effectively. Compared with the conventional TGU structure, the di/dt of the Novel-2 is improved by 56.3% at the same E-ON of 2.4 mJ/cm(2).
The gate voltage overshoot during the turn-on transient in the trench gate U-shaped (TGU) channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is investigated and novel structures are proposed for the first time with numerical simulation in this article. The TGU SOI-LIGBT features two U-shaped trench gates, G(1) and G(2), connected together. The U-shaped trench for G(2) serves as a hole barrier trench. A large number of holes accumulate in the U-shaped region during the turn-on transient because of the U-shaped architecture and the hole-blocking effect of G(2). The displacement current induced by the nonuniform distributed holes overcharges the gate and leads to high di/dt. In this article, the novel structures (Novel-1 and Novel-2) with G(2) partially filled by the polysilicon are proposed for the improvement in gate voltage overshoot while keeping superior turn-on loss (E-ON). The novel structures (Novel-1 and Novel-2) can suppress the hole accumulation and slow down the rising of the electric potential in the silicon region near the G(2). The di/dt can be lowered and the displacement current that overcharges G(2) can be effectively shielded. Compared with the conventional TGU structure, the di/dt of the Novel-2 are improved by 56.3% at the same E-ON of 2.4 mJ/cm(2).
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