A 200 μg/√Hz, 2.7 milli-g Offset Differential Interface for Capacitive Micro Accelerometer

This brief presents a switched-capacitor based low offset differential output sensor interface for MEMS capacitive accelerometers. The proposed interface employs an improved demodulation scheme by using a fully differential op-amp and a modified clocking scheme to reduce the zero-g offset. The interfacing Application Specific Integrated Circuit (ASIC) is designed and fabricated using UMC 180 nm CMOS process technology. The fabricated ASIC is integrated with a MEMS capacitive acceleration sensor and the measured results are presented. The proposed configuration achieves maximum sensitivity of 1.45 V/g with less than 2% non-linearity error. The zero-g offset is less than 3 milli-g while the noise floor is 200 mu g/root Hz approximately.

Automated summary

This brief introduces a switched-capacitor based low offset differential output sensor interface for MEMS capacitive accelerometers, which employs an improved demodulation scheme to reduce zero-g offset. The interfacing ASIC is designed and fabricated using UMC 180 nm CMOS process technology, achieving a maximum sensitivity of 1.45 V/g with less than 2% non-linearity error, a zero-g offset less than 3 milli-g, and a noise floor of approximately 200 mu g/root Hz.