Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 68, Issue 7, Pages 2478-2482Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2021.3051058
Keywords
Low power; wordline voltage generator; 3D NAND; capacitance-less charge recycling
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Funding
- National Natural Science Foundation of China [61474137]
- Provincial Hospital School Project [2019YFSY0017]
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This paper introduces a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory, achieved with boost capacitors inside the wordline voltage generator. It also proposes a multifunctional charge pump and clock control method to further reduce power consumption. Results show a significant decrease in total power consumption and maximum peak current compared to the conventional method.
This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock control method are introduced. Besides, the multifunctional charge pump also supports stage control, which can further reduce the power consumption. A wordline voltage generator with this proposed scheme has been fabricated in a 0.18 mu m BCD process, and the effective chip area is 2.4mm(2). Measurement results show that the total power consumption of Incremental Step Pulse Programming (ISPP) is reduced by 18.7% compared with the conventional one. What's more, the maximum peak current is reduced by 35%.
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