A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation

This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-hand phase noise over different supply voltages. To mitigate Delta Sigma quantization noise and PD nonlinearity effects, an FIR-filtered Delta Sigma modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 m V at 1.2 GHz. The phase noise of -97 dBc/Hz at 1-MHz offset frequency and the reference spur of -76 dBc with the programmable notch filter are achieved. The measured in-hand fractional spur levels vary from -37 dBc to -58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems.

Automated summary

This paper presents a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture with linear phase detection and technology scalability under low supply voltage. Through a specific control path and modulation method, high-performance low-voltage clock generation and modulation systems are achieved.