Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 56, Issue 6, Pages 1871-1885Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2020.3028376
Keywords
Phase locked loops; Bandwidth; Power demand; Voltage-controlled oscillators; Complexity theory; Phase noise; Computer architecture; Current matching; dynamic charge pump (DCP); low-power; offset dual-path loop; phase-locked loop (PLL); power efficiency; spur level; sub-03 V; ultra-low-voltage (ULV)
Categories
Funding
- Research and Development Program in Key Areas of Guangdong Province [2019B010116002]
- Hong Kong Innovation and Technology Fund (ITF) [GHP/004/18SZ]
- Research Grant Council General Research Fund (GRF) [16200419]
- Pioneer Hundred Talents Program, Chinese Academy of Sciences
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This article introduces an ultra-low-voltage phase-locked loop (ULVPLL) with a minimum supply voltage of 0.25 V. By utilizing an offset dual-path loop architecture and dynamic CP design, the ULVPLL achieves efficient operation at low voltages while reducing power consumption and circuit complexity.
This article presents an ultra-low-voltage phase-locked loop (ULVPLL) with the minimum supply voltage at 0.25 V. The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This significantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence, the CP voltage headroom requirement is relaxed to make the DCP be suitable for sub-0.3-V operation; meanwhile, the CP power consumption and circuit design complexity are simultaneously reduced. Implemented in 40-nm CMOS with core area of 0.00873 mm(2), the 0.15-1.6-GHz ULVPLL is capable of operation under a 0.25-0.4-V supply voltage. The power efficiency is 0.106 mW/GHz from 1.6-GHz output (at 0.4-V supply) and 0.048 mW/GHz from 0.2 GHz (at 0.25-V supply). Measured spur level is -58.3 dBc at 100-MHz offset from 1.6-GHz output (at 0.4-V supply) and -48.5 dBc at 12.5-MHz offset from 200-MHz output (at 0.25-V supply).
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