Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 56, Issue 9, Pages 2691-2700Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2021.3073976
Keywords
Calibration; Timing; Computer architecture; Time-frequency analysis; Redundancy; Prototypes; Linearity; Analog-to-digital converter (ADC); digital background calibration; sub-ranging architecture; time-interleaved (TI) ADC; timing-skew mismatch
Categories
Funding
- Samsung Research Funding Center of Samsung Electronics [SRFC-IT1502-04]
- National Research Foundation of Korea [4120200113769] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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This article introduces a relative-prime-based time-interleaved sub-ranging successive-approximation register analog-to-digital converter with on-chip background skew calibration. The calibration reduces skew and noise among the ADCs, resulting in improved performance metrics such as SFDR and SNDR.
This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular coarse ADC (C-ADC) that works as a reference ADC. To avoid the unwanted calibration tone from the reference ADC, the C-ADC is also time-interleaved to make all samples undergo the same kick back. By setting the numbers of the time-interleaved channels of the C-ADCs and F-ADCs in a relative-prime relationship, every C-ADC can be evenly shared by every F-ADC; thus, the timing skews between the interleaved sub-ADCs are calibrated by adjusting the sampling edges of every F-ADC to the particular C-ADC working as a reference ADC. An 18-channel TI 10-bit 2.2-GS/s SAR ADC was implemented as a prototype with 28-nm CMOS. Owing to the proposed on-chip background skew calibration, the peak tone by skew was reduced by 23 dB from -40 to -63 dB, which corresponds to the residual skew reduction from 1.6 ps to 113 fs near the Nyquist input. Thus, the prototype ADC achieved a spurious free dynamic range (SFDR) over 52.8 dB and a signal-to-noise-and-distortion ratio (SNDR) over 44.9 dB with 18.2-mW power consumption, which leads to a Walden figure-of-merit (FoM) of 57.8 fJ/conversion-step.
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