Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 56, Issue 8, Pages 2347-2359Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2021.3057372
Keywords
Analog-to-digital converter (ADC); boot-strapped switch; digital-to-analog converter (DAC); gradient; high-speed ADC; matching; parasitic capacitance; successive-approximation register (SAR) ADC; time-interleaved ADC
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Funding
- Ministry of Science and Technology, Taiwan [MOST 106-2622-8009-017]
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This ADC features advanced techniques such as modern DAC design, quantized sub-radix-2 scaling, and a high-speed dual-path bootstrapped switch, resulting in a performance level higher than other similar products.
An 8-bit 10-GHz 8x time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts.
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