Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications

Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here, we report on sharp current jumps and stable hysteretic loops in the drain current as a function of gate voltage V-G for both n- and p-type commercial-foundry 180-nm-process CMOS transistors when operated at voltages exceeding 1.3V at cryogenic temperatures. The physical mechanism responsible for the device bistability is impact ionization charging of the transistor body, which leads to effective back-gating of the inversion channel. This mechanism is verified by independent measurements of the body potential. The hysteretic loops, which have a >10(7) ratio of high to low drain current states at the same V-G, can be used for a compact capacitorless single-transistor memory at cryogenic temperatures with long retention times. Published under an exclusive license by AIP Publishing.

Automated summary

This research reveals sharp current jumps and stable hysteretic loops in drain current at cryogenic temperatures when operating CMOS transistors at voltages exceeding 1.3V. The mechanism responsible for device bistability is impact ionization charging, leading to effective back-gating of the inversion channel. This phenomenon can be utilized for compact capacitorless single-transistor memory with long retention times.