A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

Automated summary

Simultaneous Escape Routing (SER) refers to escaping circuit pins simultaneously from inside two or more pin arrays. Existing studies have not addressed this issue, highlighting the need for automated routing algorithms to tackle this difficult task. The proposed algorithm outperforms existing state-of-the-art algorithms in terms of routability and time consumption, achieving 99.9% routability and independence of grid topology and component pin arrangement.