4.7 Article

Controllable potential barrier for multiple negative-differential-transconductance and its application to multi-valued logic computing

Journal

NPJ 2D MATERIALS AND APPLICATIONS
Volume 5, Issue 1, Pages -

Publisher

NATURE PORTFOLIO
DOI: 10.1038/s41699-021-00213-4

Keywords

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Funding

  1. Samsung Research Funding & Incubation Center of Samsung Electronics [SRFC-MA1701-02]

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Research on multi-valued-logic (MVL) computing has been reinvigorated recently due to the demand for greater power saving in current logic technologies. This study focuses on implementing a multiple negative-differential-transconductance (NDT) phenomenon in a van-der-Waals multi-channel phototransistor through control of partial gate potential and light power/wavelength, demonstrating its potential application as a core device in MVL arithmetic circuits.
Various studies on multi-valued-logic (MVL) computing, which utilizes more than two logic states, have recently been resumed owing to the demand for greater power saving in the current logic technologies. In particular, unlike old-fashioned researches, extensive efforts have been focused on implementing single devices with multiple threshold voltages via a negative-differential current change phenomenon. In this work, we report a multiple negative-differential-transconductance (NDT) phenomenon, which is achieved through the control of partial gate potential and light power/wavelength in a van-der-Waals (vdW) multi-channel phototransistor. The partial gating formed a controllable potential barrier/well in the vdW channel, enabling control over the collection of carriers and eventually inducing the NDT phenomenon. Especially, the strategy shining lights with different powers/ wavelengths facilitated the precise NDT control and the realization of the multiple NDT phenomenon. Finally, the usability of this multiple NDT device as a core device of MVL arithmetic circuits such as MVL inverters/NAND/NOR gates is demonstrated.

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