Influence of the SiC/SiO2 SiC MOSFET Interface Traps Distribution on C-V Measurements Evaluated by TCAD Simulations

The reduction of the trap density at the SiC/SiO2 interface of a SiC metal-oxide-semiconductor field-effect transistor (MOSFET) is still an open issue for development of the next generation. Since TCAD simulations are one of the most powerful tools adopted in the field of power semiconductor devices, in this article, we define the guidelines for the calibration of the TCAD model from the point of view of the interface traps modeling. We have carried out a qualitative analysis of the effect of the SiC/SiO2 interface traps properties on the C-V curve by means of TCAD simulations, to support the interpretation of the experimental C-V curves of a SiC MOSFET. A new approach for the simulation of the C-V curves of a SiC MOSFET is proposed as well. The aim of this article is the analysis of the effect of the SiC/SiO2 interface traps on the C-V curve by means of TCAD simulations.

Automated summary

This article focuses on the analysis of the effect of SiC/SiO2 interface traps on the C-V curve of a SiC MOSFET through TCAD simulations, as well as proposing guidelines for the calibration of the TCAD model. Qualitative analysis of the impact of SiC/SiO2 interface traps properties on the C-V curve was conducted using TCAD simulations to support the interpretation of experimental C-V curves, and a new approach for simulating the C-V curves of a SiC MOSFET was introduced.