Electrostatic characterization and threshold voltage modeling of inversion type InGaAs gate-all-around MOSFET

This paper presents an analytical investigation of the electrostatic properties of a moderately doped symmetric gate-all-around nanowire MOSFET having InGaAs channel. The model is continuous from depletion to strong inversion regime that circumvents regional approach, thus smoothly capturing the transition of the charge profile in all regions of operation. The evolution of the model is facilitated by the solution of quasi 2-D Poisson equation with appropriate boundary conditions in a square gate-all-around geometry, incorporating fixed oxide charge and interface trap defects. The determination of mobile charge density leads to the capacitance-voltage (CV) characteristics as a function of gate bias. The CV profile is investigated subject to scaling of physical parameters and material properties. Further, a threshold voltage model is presented for a long channel gate-all-around device that utilizes the well-known double derivative method. This model accurately predicts the threshold voltage variation with fin width, oxide thickness and channel doping, highlighting room for further improvement in electrostatics by incorporating high-k dielectric. The excellent match between the model results and TCAD simulation reflects the validity of the proposed model.

Automated summary

This paper presents an analytical investigation of the electrostatic properties of a moderately doped symmetric gate-all-around nanowire MOSFET with InGaAs channel. The model covers depletion to strong inversion regime continuously, facilitating the determination of mobile charge density and capacitance-voltage characteristics. By incorporating various physical parameters and material properties, the threshold voltage model accurately predicts the threshold voltage variation, highlighting the potential for further improvement in electrostatics.