Cache performance of NV-STT-MRAM with scale effect and comparison with SRAM

Cache is the bridge between CPU and memory for data exchange, which consumes up to 45% of the entire CPU energy. Low power cache and memory are urgently required for the computer system. The paper focuses on using Destiny to simulate the scaling roadmap of the STT-MRAM. The performance evaluation of the STT-MRAM is explored in the cache applications, including the cell area, the aspect ratio for different cache capacities. Based on the exploration, optimisation on the performance is achieved, showing a write latency reduction of up to 5.4% and a total leakage power reduction of up to 42.1%, suggesting an important application scenario for the STT-MRAM. Furthermore, comparison is conducted in the cache performance between SRAM and STT-MRAM using high performance (HP) and low power performance (LOP) device models, including the capacity, total area, hit latency, write latency, total leakage power, hit dynamic energy and write dynamic energy. It is interesting to disclose that the STT-MRAM memory bank with large-capacity (> 32 MB) shows better performances. The large cache with the STT-MRAM exhibits better performances than the cache based on the SRAM. Especially for the STT-MARM using LOP device model compared with the SRAM using LOP device model, it can effectively reduce energy consumption.

Automated summary

The paper focuses on simulating the scaling roadmap of STT-MRAM using Destiny and explores its performance evaluation in cache applications. It shows that STT-MRAM can achieve performance optimization under certain conditions, with large-capacity memory banks performing better and LOP device model effectively reducing energy consumption.