Journal
IEEE TRANSACTIONS ON ULTRASONICS FERROELECTRICS AND FREQUENCY CONTROL
Volume 68, Issue 4, Pages 1437-1441Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TUFFC.2020.3033761
Keywords
Logic gates; Capacitance; Transconductance; Temperature; Tunneling; Semiconductor process modeling; TFETs; Ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET); memory window; negative capacitance; temperature
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This study presented a numerical simulation of the Ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET), analyzing its performance and temperature sensitivity around the Curie temperature. Results showed that the Ferro-TFET outperforms conventional TFETs and MOSFETs in reducing mobility degradation and performance loss at high gate voltage and temperatures. Operating at the Curie temperature, the Ferro-TFET demonstrates remarkable advantages for analog and RF applications.
In this article, a numerical simulation study for the ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET) has been presented. The performance of the device is analyzed following Landau's theory and its behavior in the temperature range of 200-300 K. A minimum subthreshold swing and maximum transconductance is obtained around the Curie temperature (T-C) of 580 +/- 10 K for the simulated device. The simulation result is supported by the simple analytical model. The temperature sensitivity analysis is studied on different analog and RF figure of merits for Ferro-TFET. In this study, the Ferro-TFET shows the remarkable result in reducing the detrimental effect of mobility degradation at high gate voltage and performance degradation at high temperatures as compared to conventional TFETs and MOSFET. Therefore, at Curie temperature, the operation of the Ferro-TFET shows the remarkable results for analog and RF applications.
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