4.6 Article

Hardware-in-the-Loop and Field Validation of a Rotor-Side Subsynchronous Damping Controller for a Series Compensated DFIG System

Journal

IEEE TRANSACTIONS ON POWER DELIVERY
Volume 36, Issue 2, Pages 698-709

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPWRD.2020.2989475

Keywords

Doubly fed induction generators; Impedance; Rotors; Stators; Damping; Resistance; Wind power generation; DFIG; field validation; hardware-in-the-loop tests; rotor-side converter; subsynchronous control interaction; subsynchronous oscillation

Funding

  1. National Natural Science Foundation of China [51737007, 51925701]
  2. UNSW-Tsinghua Collaborative Research Fund [2020Z02NSW]

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Several incidents of subsynchronous control interaction (SSCI) have occurred in large-scale grid-interfaced doubly-fed induction generator (DFIG) based wind farms in the past decade. This paper validates the performance of a practical rotor-side subsynchronous damping controller (RSDC) through controller hardware-in-the-loop (CHIL) simulations and real-world DFIG tests, demonstrating its ability to suppress SSCI and enhance confidence in the mitigation strategy based on converter control modifications.
In the past decade, several subsynchronous control interaction (SSCI) incidents have been reported in various large-scale grid-interfaced doubly-fed induction generator (DFIG) based wind farms. The subsynchronous oscillation caused by the SSCI endangers the safe and reliable operation of wind power systems. The DFIG's converter controls play a crucial role in such interactions; therefore, several SSCI mitigation schemes have been reported, which modify the DFIG's converter controls to stabilize the subsynchronous oscillation caused by the SSCI. However, the effectiveness of such converter control modifications has not been verified through laboratory or field experiments. This paper considers a practical rotor-side subsynchronous damping controller (RSDC) and fills the gap by first validating the RSDC's performance through controller hardware-in-the-loop (CHIL) simulations, and then implementing it in a real-world DFIG connected to a series compensated line. The RSDC fundamentally reshapes the effective impedance of the DFIG to stabilize the subsynchronous oscillation. The CHIL simulations, as well as the field tests, successfully validated the RSDC's ability to suppress the SSCI. The results enhanced the practical confidence of the SSCI mitigation strategy based on RSC's converter control modification.

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