Journal
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Volume 69, Issue 5, Pages 2697-2711Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMTT.2021.3061560
Keywords
Bluetooth-low energy (BLE); CMOS; currentreuse; direct-conversion receiver; receiver (RX); subthreshold; ultralow -power wireless
Categories
Funding
- Qualcomm Inc.
- Natural Sciences and Engineering Research Council of Canada (NSERC)
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An ultralow-power direct-conversion Bluetooth-lowenergy (BLE) receiver front-end utilizing current-reuse and subthreshold techniques exhibits excellent performance in terms of noise figure and gain, meeting system specifications over PVT variations. The prototype, implemented in a 40-nm LP CMOS process, features a small silicon area and robustness against process, voltage, and temperature variations.
An ultralow-power direct-conversion Bluetooth-lowenergy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 mu W and achieves a noise figure (NF) of 3.2-dB and a high gain ( programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of -95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at -19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83 degrees with spot phase noise of -119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6-mu W automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple mu W-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm(2).
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