Journal
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 68, Issue 5, Pages 3865-3875Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2020.2984999
Keywords
Phase locked loops; Frequency estimation; Frequency locked loops; Harmonic analysis; Estimation; Synchronization; Frequency synchronization; Distorted voltage; frequency-locked loop (FLL); phase-locked loop (PLL); synchronization
Categories
Funding
- Khalifa University
- Massachusetts Institute of Technology (MIT), Cambridge, MA, USA [02/MI/MIT/CP/11/07633/GEN/G/00]
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This article focuses on enhancing the performance of a single-phase PLL under distorted supply voltage conditions by proposing a type-1 frequency-fixed FLL. The proposed FLL utilizes an improved low-pass filter with notch characteristics and selective harmonic filtering technique to suppress double-frequency oscillation and compensate phase offset error, making it robust for grid synchronization of single-phase converters. Experimental results validate the performance improvement achieved by the proposed FLL.
Phase-locked loops (PLLs) are widely used for the synchronization of power electronic based equipment due to their ease of digital implementation and satisfactory response. This article focuses on a single-phase PLL to enhance its performance under distorted supply voltage condition. In most single-phase PLLs, the loop filter used within the control loop cannot completely reject low-order harmonics. Thus, the distortion in supply voltage significantly affects the frequency and phase estimations, both in steady-state and dynamic conditions. To overcome these problems, this article proposes a type-1 frequency-fixed frequency-locked loop (FLL). Generally, when the frequency is fixed in a PLL or FLL, the estimated variables (frequency and phase) suffer from double-frequency oscillation and phase offset whenever the system experiences any frequency variation. In the proposed work, a modified low-pass filter with notch characteristics is used to reject the double-frequency oscillation while the phase offset error is compensated by adding the linearized phase error to the estimated phase angle. Furthermore, a selective harmonic filtering technique is incorporated to improve the disturbance rejection capability under distorted conditions. These advantages make the proposed FLL robust for grid synchronization of single-phase converters. Experimental results are provided to verify the performance of the proposed FLL.
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