Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 68, Issue 4, Pages 1471-1477Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3062251
Keywords
3-D integration; half-select programming; interconnects; nano-electro-mechanical (NEM) switches; nonvolatile (NV) memory (NVM)
Funding
- Center for Energy Efficient Electronics Science, National Science Foundation (NSF) [0939514]
- Berkeley Emerging Technologies Research Center
- NSF [1752814]
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Design tradeoffs for vertically oriented nonvolatile (NV) nano-electro-mechanical (NEM) switches implemented using multiple interconnect layers in a 5-nm-generation CMOS back-end-of-line (BEOL) process are investigated via 3-D device simulation. It is found that sub-20-ns programming delay is possible with programming voltages compatible with standard input-output (I/O) CMOS circuitry, and that the write energy of an NV-NEM bit-cell will be less than 5 aJ. A crossbar array architecture operated with a half-select row/column bit-cell programming scheme is effective for avoiding write disturbance.
Design tradeoffs for vertically oriented nonvolatile (NV) nano-electro-mechanical (NEM) switches implemented using multiple interconnect layers in a 5-nm-generation CMOS back-end-of-line (BEOL) process are investigated via 3-D device simulation. Programming pulse voltage and width operating windows are identified for avoiding catastrophic pull-in. The simulation results indicate that sub-20-ns programming delay is possible with programming voltages compatible with standard input-output (I/O) CMOS circuitry, and that the write energy of an NV-NEM bit-cell will be less than 5 aJ. A crossbar array architecture operated with a half-select row/column bit-cell programming scheme is found to be effective for avoiding the issue of write disturbance.
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