Jitter-Power Trade-Offs in PLLs

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.

Automated summary

This paper investigates the basic relationship between jitter and power consumption, highlighting potential severe issues when jitters fall below 10 fs. It also suggests that clock generation in analog-to-digital converters may consume more power than the converter itself.